Interlock System Response Time

The interlock system must be capable of detecting the process hazard and responding in time to
prevent the hazardous event.

For local functions involving only one controller this means for example, performing the following actions:

1. Sense the out-of-control condition
2. Digital filtering of input signal
3. Input process scan time
4. PLC program scan time
5. Any trip delay timers set to remove process noise must time out
6. Output process scan time
7. Digital filtering of output signal
8. Fully actuate the output device

Interlock System Response Time

If several controllers are involved in the interlock function (central functions or local functions involving
several controllers), the communication time and the PLC program scan time for each controller must
be added.

How much time the interlock system has to respond depends on the process dynamics and the
conditions initiating its actions. The process safety time available for any given safeguard starts when it
is required to take action and ends at the point where the event can no longer be mitigated.

The process safety time is defined as the time period between a failure occurring in the process or the
basic process control system (with the potential to give rise to a hazardous event) and the occurrence
of the hazardous event if the safety instrumented function is not performed.

Given the degree of uncertainty in the process safety time, the interlock system should be capable of
completing its action within one-half of its allocated process safety time.

The time to react is defined for each interlock function. It determines the techniques to be used for the
implementation of the function. The time to react is the time elapsed between the risk materialization
and the request for mitigating action is issued.

Slow profile

If the time to react for a local function is above 200ms and 1s for a central function, standard industrial
control techniques like PLCs can be used.

Fast profile

If the time to react for a local function is below 200ms and 1s for a central function, functions will be
implemented by faster but more expensive and difficult to deploy techniques like FPGAs.

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